PPRuNe Forums - View Single Post - Parallel electrical systems, the synchronising bus and ATPL theory’s wisdom thereto
Old 27th Apr 2016, 11:58
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CReed
 
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I can see that either fault could have been caused by a failure of the voltage regulator. I suppose that an over excitation could have also been caused by something more hazardous such as CSDU overspeed. Both questions state however that it is a persistent fault. Since the over-excitation could pose a fire risk, I believe it would be necessary to first trip the ECB and then trip the GCB to prevent reverse current flow from the busbar. This may follow CSD disconnect.

In the case of the under-excitation fault, I think that the GCB would be tripped first and if the fault persisted, as it is supposed to have done, the ECB would be tripped.

In both cases, reactive (and in the event of a CSD overspeed, real loads too) loads would become unbalanced, requiring isolation of the AC bus from the synchronising bus by the BTB. However, once the GCB is opened, which would seem to be the case in both scenarios, I don't see why this would be necessary, so long as the fault is not with the busbar itself. Is the correct answer suggesting that the protection device only opens the BTB transiently?

Furthermore, is the question I posted in my previous response, about a "top excitation limit fault" not asking the same thing as the second question in my original post about an "over excitation limit fault"?

Anyway, thank you for your help, but I'm really struggling to understand this and since it would seem that I've still got it wrong, I'd really appreciate if you could explain it for me.

Kind regards

Charlie
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