http://www.hursts.eclipse.co.uk/airb...rmal/notes.pdf
5.7.*SFCC faults
Each SFCC has fully independent slat and flap channels. A failure of a channel in a single controller will lead to slow operation of the associated surfaces. In addition, the flap channel of SFCC1 provides input to the idle control part of the FADECs and to the EGPWC.
Failure of both flap channels or failure of both slat channels is covered in Section*5.6, “Flaps and/or slats fault/locked”.
[F/CTL*FLAP(SLAT)*SYS*1(2)*FAULT, FCOM*1.27.50.3000, FCOM*3.2.27.5000, FCOM*3.2.27.6000]
Looks like the output of SFCC1 is fed to the FADECs, so the restriction is to prevent the possibility of bad data interfering with thrust operation. Not sure about SFCC2, but it may be a a precautionary measure.
Unless we're talking about SFCC1's flap channel (is that channel 1 or 2?), in which case the writeup makes sense as is.