Originally Posted by
Piper_Driver
Our solution was to use error detecting and correcting memory. This architecture used extra memory bits that would allow any single bit error in a memory word to be corrected on the fly.
…. Does anyone know if memory correction technology was used on the Boeing flight control computers? If so it would rule out random bit flips as an error condition.
No, this only protects against bit-flips in memory, there is also a risk that the CPU registers get corrupted.
For this you need two ordinary CPU’s, or a lock-step CPU like TMS570.
A lock-step CPU has Error CorreCtion on memory, and two CPU’s running as one.
The second CPU runs the same machine code instructions as the first one, but one clock cycle delayed.