Originally Posted by
ve3id
This is not a new feature, it was available on the PDP11 way back in the eighties when I was an FE on DEC hardware!
I have no experience with that, so I can't comment on it, but at least in the x86 world you needed additional hardware to do that, for example DMA controllers. With PCI that changed, each PCI device could take control of the bus when it needed it, unless another device was using it. Of course it's not really that simple, there is still the chipset managing that and preventing conflicts.
There are a lot of variations on this theme, the most recent being I/O devices that can write directly to the CPU cache memory to improve performance even further. Anyway got too carried away, sorry for going off topic.