Boeing 787s must be turned off and on every 51 days
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Because maybe it has nothing do with a fixed period of time? Maybe there is a cache or a temporary log etc. that gets updated regularly and a some new data is attached. After 51 days the storage that is used for this activity is full and the system crashes. Just one example.
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That's more than 3 words . . .
Back you your area of speciality, if you have one . . .
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Good to see it isn't just us. Our modern locomotives have dozens of computers running everything from the diesel engine & traction power systems to crew displays, signalling and ATP. I've lost count of the number of BOBO (Battery off, wait a bit, battery on) reboots I've had to do to try to get them talking to each other again!
You could have just left it at "I can't explain", then three words would indeed have sufficed.
Counters, and microprocessor registers in general, typically have a capacity that corresponds to some multiple of 8 bits.
For example a 16-bit counter isn't capable of counting beyond 65,535 (one less than 2^16). Using one for an application that requires counting to values higher than that will produce unpredictable results.
In the case of the 787 issue, whatever the maximum value that the counter can accommodate is (2^32 is being suggested, equivalent to 4,294,967,295 clock ticks), that value is reached after approximately 51 days.
For example a 16-bit counter isn't capable of counting beyond 65,535 (one less than 2^16). Using one for an application that requires counting to values higher than that will produce unpredictable results.
In the case of the 787 issue, whatever the maximum value that the counter can accommodate is (2^32 is being suggested, equivalent to 4,294,967,295 clock ticks), that value is reached after approximately 51 days.
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A common tick counter period in real-time systems is 1.024 ms (don't ask me why!). That works out at 50.9 days
Real-time systems interfacing directly with hardware are often have much faster system tick and OS preemptive interrupts.
And almost all CPU's today have a clock faster than 16MHz. (i.e. prescaler values need to be larger than 2^14 to divide to 1ms. )
For PC hardware google High Precision Event Timer and cpu Time_Stamp_Counter
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I forgot that most modern CPUs are clocked to give a reliable 1 microsecond interval.
That means that an interrupt coded to click every millisecond is actually triggered every 2^10 microseconds or 1.024 millisecond.
That is the reason.
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Counters, and microprocessor registers in general, typically have a capacity that corresponds to some multiple of 8 bits.
For example a 16-bit counter isn't capable of counting beyond 65,535 (one less than 2^16). Using one for an application that requires counting to values higher than that will produce unpredictable results.
In the case of the 787 issue, whatever the maximum value that the counter can accommodate is (2^32 is being suggested, equivalent to 4,294,967,295 clock ticks), that value is reached after approximately 51 days.
For example a 16-bit counter isn't capable of counting beyond 65,535 (one less than 2^16). Using one for an application that requires counting to values higher than that will produce unpredictable results.
In the case of the 787 issue, whatever the maximum value that the counter can accommodate is (2^32 is being suggested, equivalent to 4,294,967,295 clock ticks), that value is reached after approximately 51 days.
Of course the reset happens automatically every time the aircraft is powered down. It sounds like it never occurred to Boeing or the FAA that you could have a scenario where an aircraft was continuously powered-up for 51 days or more, and I'm struggling too to imagine that actually happening.
