Originally Posted by
groundbum
as an IT engineer this changing from flip-flop to dual reduandancy is massive, and unless work started years ago will NOT be ready for September. And if it has been rushed then it needs full end to end testing as it's such a fundamental change. There's a philosophy in coding that for every 2 things you fix, you break something else. It's the nature of the beast.
G
This is known as "Single Event Upset" or SEI. Although rare, as processors and memory get smaller and more dense, the probability of SEI goes up. In early FADECs, SEI was pretty much unheard of, during the 747-8 flight testing we found evidence of SEI a little less than once very 100 aircraft flight hours (four engines, two channels per FADEC).
SEI is fairly easy to deal with in modern FADECs. Basically, you do continuous parity or check-sum checks - if it suddenly fails the check it's assumed to be SEI and the channel resets (a reset takes about a second, the other channel will take over if necessary - worse case there may be a short, temporary thrust loss if the opposite channel is incapable of taking over). However the continuous checking has a small impact on the processor throughput capability - if they are already close on throughput margin, adding the checks could be a problem.